LDPC Encoder (X026)

The LDPC chip implements two low-density parity-check (LDPC) codes: a 4K code and an 8K code. For certain applications, LDPC coding can provide high bandwidth efficiency.

Highlights

• Selectable 4K and 8K encoders
• 1 Gbit/s data rate at 67 MHz
• Parallel 16-bit input and output
• 2.5 V core voltage
• TID > 100 krad
• SEL immune to 120 MeV·cm²/mg LET
• Typical power usage 1.3 W at 67 MHz
• Qualified to Level-1 space mission requirements

Description

The LDPC chip implements both a 4K LDPC code and an 8K LDPC code.

LDPC 4K code

The (4088,3360) LDPC code is shortened from a geometry-based (4095,3367) cyclic code designed to have an error floor no higher than 10⁻¹⁰ BER. The code is specified by a polynomial of order 728. The polynomial is the reciprocal polynomial of the (0,6)th-order Euclidean geometry code based on Euclidean geometry EG(2,26).

Message data is input to the chip 16 bits at a time to allow a 16-bit look-ahead scheme. By using look-ahead, a 1 Gbit/s bit rate can be sustained using a 67 MHz system clock. The 210 16-bit data words are input to the chip and passed out with 6 clock cycles of latency when no frame marker is inserted. When the two-word frame marker is prepended, data has an 8-clock-cycle latency. After the message words, forty-six 16-bit parity words follow, of which 45 are all parity bits. The final 16-bit output word contains the last 8 bits of parity with zeros appended.

LDPC 8K code

The (8158,7136) LDPC code is shortened from a geometry-based (8176,7154) quasi-cyclic code designed to have an error floor no higher than 10⁻¹⁰ BER. The code is specified by an 8176 × 1022 H matrix. Message data is input to the chip 16 bits at a time. A 1 Gbit/s bit rate can be sustained using a 67 MHz system clock.

The 446 16-bit data words are input to the chip and passed out with 10 clock cycles of latency when no frame marker is inserted. When the two-word frame marker is prepended, data has a 12-clock-cycle latency. After the message words, sixty-four 16-bit parity words follow, of which 63 are all parity bits. The final 16-bit output word contains the last 14 bits of parity with zeros appended.